AHCAL Testbeam Campaign at CERN 2015 (July/August)

Operation and useful information related to the July/August AHCAL testbeam campaign at CERN. For more general information or for previous testbeam periods, go to tb2015.

Feel free to contribute or to correct anything (in this case, please send me a mail so I can know what was wrong adrian.irles@desyNOTSPAM.de ), or to ask me to do any change.

Contents

Setup

July 2015

In July, we have take data in the H2@SPS line at CERN, during the period between the 08/07/2015 to the 22/07/2015.

Our setup consisted in a steel absorber structure (thickness 17.2 mm!) with 14 layers. Ordered as follow (first is the closest to beam):

SteelAbsorberStructure.png

Phys.
order

Module#

power
cable

HDMI
cable

MPOD

LDA
port#

name

1.

1

01

01

u0,u100,u400

00

EBU_0

2.

3

03

03

u2,u102,u402

01

EBU_2

3.

M

04

04

u3,u103,u403

02

Mainz

4.

11

05

05

u4,u104,u404

03

HBU2_14

5.

10

06

06

u5,u105,u405

04

HBU2_13

6.

9

07

07

u6,u106,u406

05

HBU2_X

7.

8

08

08

u7,u107,u407

06

HBU2_VI

8.

7

09

09

u200,u300,u500

07

HBU2_VII

9.

6

10

10

u201,u301,u501

08

HBU2_VIII

10.

5

11

11

u202,u302,u502

09

HBU2_IX

11.

12

12

12

u203,u303,u503

10

"Ketek"

12.

13

13

13

u204,u304,u504

11

"Ketek new"

13.

14

14

14

u205,u305,u505

12

"Sensl"

14.

15

15

15

u206,u306,u506

13

"Sensl"

Detector_layout.png

See K. Krueger slides for a more extensive report, and follow the next link to see some me of us during installation at H2@SP

August 2015

The second period (actually ongoing) goes from the 12/08/2015 to the 26/08/2015. In this occasion we are located in the H6 beam line (also at SPS) and our setup uses tungsten absorbers instead of steel. You can see here an schematic picture of our stack:

TungstenAbsorberStructure.png

In this case, we have one more EBU layer. The EBUs are then place as the following : EBU_0 (horizontal type) outside of the stack. EBU_1 (vertical type) in the first place in the stack and EBU_2 (horizontal type) in the second place in the stack. This is done in order to make use of the strip splitter algorithm. This is summarized in the following description, and in the next table that shows relavant information related to the cabling, positioning and namig of the layers. The order of the description is the same than the first column in the table.

Phys.
order

Module#

power
cable

HDMI
cable

MPOD

LDA
port#

name

1.

1

01

01

u0,u100,u400

15

EBU_0

2.

2

16

02

u207,u307,u507

00

EBU_1

3.

3

03

03

u2,u102,u402

01

EBU_2

4.

M

04

04

u3,u103,u403

02

Mainz

5.

11

05

05

u4,u104,u404

03

HBU2_14

6.

10

06

06

u5,u105,u405

04

HBU2_13

7.

9

07

07

u6,u106,u406

05

HBU2_X

8.

8

08

08

u7,u107,u407

06

HBU2_VI

9.

7

09

09

u200,u300,u500

07

HBU2_VII

10.

6

10

10

u201,u301,u501

08

HBU2_VIII

11.

5

11

11

u202,u302,u502

09

HBU2_IX

12.

12

12

12

u203,u303,u503

10

"Ketek"

13.

13

13

13

u204,u304,u504

11

"Ketek new"

14.

14

14

14

u205,u305,u505

12

"Sensl"

15.

15

15

15

u206,u306,u506

13

"Sensl"

It is always a good idea to check if the numbers are correct. Status as of Aug 11. TO BE CHECKED!!!

DAQ Hierarchy

Current data adquisition is the fruit of several years of improvement in testbeam and in lab. The task of the data adquisition system is to readou the data from the ASICs and also to control the detector (slow control files, acquisition control...). Moreover, the goal is to test a DAQ that can be used for testbeam and also for ILD which actually have completely different time requirements. The current engineering prototype emulates one of the barrel regions of the AHCAL, and incorporates the design of the LDA that would be used in the real detector. Here we can se a schematic view of the hadronic calorimeter in the ILD and our engineering prototype:

ILD_prototype

The current DAQ hierarchy is as follows:

hyerarchy

ASIC (SPIROC 2b, Omega group)

SPIROC is a dedicated very front-end for an ILC prototype hadronic calorimeter with SiPM readout. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analog memory array with a depth of 16 for each is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analog memory contents (time and charge on 2 gains). The data are then stored in a 4kbytes RAM. A very complex digital part has been integrated to manage all theses features and to transfer the data to the DAQ.

Detector Interface (DIF)

The detector interfacemanages communication between the all the ASICS, the power board (with generates most voltages needed for the operation) and the calibration board (which controls the LED gain calibation system). It collects the data from all the ASICs and sends the data to the LDA. The comunication is made through HDMI (links at 10 Mbit/s, UART like). The DIF also features inputs for external trigger, spill, and validate signals.

Link Data Agregator (LDA)

In current testbeam period we are using a Wing LDA designed @Uni Mainz specifiquely to the AHCAL geometry and using MicroHDMI connectors. The software and firmware has been developed together at DESY and FZU (Prague)

Clock and Control Card (CCC)

The CCC provides the master clock of the DAQ and starts and stops the acquisition according to the spill level and readiness of all ASICs.

It receives the trigger validation signal and the spill signal and distribute them.

More info can be found inthese slides.

Trigger, T0, Cherenkov channels and spill signal

The AHCAL runs in autotrigger (or triggerless) mode when we are taking beam data. This means that all hits above certain "autotrigger" threshold are stored (data acquisition stops as soon as one of the ASIC has memory full - BUSY-). This has the clear disadvantage of result in a very noise sensitive detector. For that, we use external triggers to validate the hits:

T0 channels

We use a external scintillator coincidence to validate events. The coincidence signals is injected into a bunch of chosen channels (T0 channels). The posteriori event reconstruction is done using this information: events in the same Bunch Crossing ID (BX or BunchXID) are kept if one (or few) of the T0 channels have signal. In practice: there is a validation gap of ~200 ns at the end of each BX where all hits are accepted but there is no direct way to know if a hit has been validated or not, except the TDC information that tell us at which time of the BX the hit occurred.

The list of these channels is:

List of T0 channels

Name

Module#

ChipId

Channel

Comments

Ketek

12

169

29

-

Ketek

12

177

23

-

Ketek new

13

185

29

-

SenSL

14

201

29

noisy in few runs

SenSL

14

211

6

broken

SenSL

15

217

23

-

Cherenkov channels

Similarly, we can use a injected signal from a Cherenkov discriminator which has been tuned to trigger electron events and discriminate pions and kaons.

The list of these channels is:

List of Cherenkov Channels

Name

Module#

ChipId

Channel

Comments

HBU2_IX

5

141

29

-

Ketek new

13

195

12

noisy

SenSL

15

227

6

-

Spill structure

The DAQ was designed for the ILC operation, which means, that the spill (particle collisions) is shorter than the readout cycle. The spill is ~1ms long in the ILC mode and the distance between spills is 199 ms. However, the spill is much longer at PS (~400 ms) and SPS (~4.8 s) and the particle rate is not that high. The ASIC is therefore configured in theTestbeam mode, where the bunch-crossing clock is only 250 kHz (compared to 5 MHz in ILC mode) and the acquisition has to be restarted as soon as all data from all DIFs are transferred to the LDA (compared to fixed timing in the ILC mode).

The Acquisition cycle has following structure: Acquisition --> ASIC Conversion --> ASIC-DIF data transfer --> DIF-LDA data transfer.
The Busy signal is raised as soon as the Acquisition has finished (ASIC memory is full) and is ceased once the data transfer is finished. The ASIC is then ready to start a new acquisition cycle.

The acquisition cycle is typically 1~3 ms long in the Testbeam mod. The "dead time" (conversion, data transfer) is 45~80 ms, depending on the data occupancy. As a result, we take 80~90 readout cycles per SPS spill on average.

The picture below shows the typical timing at PS in 2014, which was also combined with the SiECAL layer, which used the same CCC start acquisition command in order to achieve the defined timing.
Spill

Electronic setup and cabling: diagrams and pictures

You can find find here the diagrams of our electronic setup at the testbeam area and at the hut at H6 (please not that the colors are used just for cosmetic reasons). We divided our electronic modules in three racks: one at the hut and two at the testbeam area.

Testbeam Area:

TBAreaElectronics1 TBAreaElectronics2

TBAreaElectronics3 TBAreaElectronics4

Hut:

HUTElectronics1 HUTElectronics2

Common DAQ: EUDAQ

The EUDAQ is a modular and portable Data Adquisition (DAQ) framework. It was originally deveopped for pixel telescope in the ILC targeted EUDET initiative and since then successfully and widely used by LHC community too. In a nuthsell, it is splitted in a number of different processes, each comunicating with TCP sockets:

  1. Central Run Control
    • an interface to control all the DAQ: sends the start/stop commands and the configuration settings the system,
    • the other processes connect to the Run Control to receive commands and send their status.
  2. Producer processes:
    • Each piece of hardware (that produces data) will have a Producer process associated to configure the hardware, read the data and send them to the Data Collector.
  3. Data Collector:
    • Receives all the data streams from the producers and combines them into single strem.

One of the main features of the EUDAQ is that its flexibility to convert the raw output data to other formats, like lcio format, for example. It also brings the possibility to construct an Online Monitor to study the ongoing runs during data taking. This feature has been not implemented for this testbeam period.

We can use the EUDAQ to slave the individual DAQ systems (AHCAL WingLDA + CCC, for example). In this case, the EUDAQ sends the START/STOP commands to the different DAQs and collects all streams of data to convert them to a more maneagle format (lcio) and save them in one file directly during the data taking. This was tested and first time used in December 2014 test beams at CERN, where the Si-Ecal and de Scintillator AHCAL run together very succesfully. In this case, the CCC of the scintillator (with clock period that contain the clock of the Si-ECAL) slaved the CCC of the Si-ECAL by sending it a global clock signal and the spill signal, defining in this way the clock of the whole system. The EUDAQ, then, connects with the two pc's that manage each DAQ independently. This is shown schematically in the figure and also in the Spill Structure section

Eudaq Hierarchy

In the testbeam period described in this wiki only the Sicintillator AHCAL is managed by the EUDAQ.

We are currently working with version EUDAQ1.4.5, in a CentOS7 machine. The manual for this version can be read here.

Data

Full infromation of the taken data is available in the elog

At the data is stored in two different formats:

Data access

If you want to have access to the data :

The data is stored here :

For grid people

For DESY on the NAF2

You might need to get 7zip to unpack data (http://p7zip.sourceforge.net/). I already compiled the tool here : /nfs/dust/ilc/user/ebrianne/p7zip/7za.

I am currently preparing a script (using the script written by Roman for the physics prototype) to copy data from the Labview PC first (txt) then the EUDAQ (slcio) automatically to dCache.

For previous data, it is available here :

/grid/calice/tb-desy/native/desyAhcal2015/AHCAL_Testbeam_RAW_XXX_2015 or /pnfs/desy.de/calice/tb-desy/native/desyAhcal2015/AHCAL_Testbeam_RAW_XXX_2015

July

You can find some nice eventdisplays and hitmaps in Katja's talk.

August

Operation

Shifter tasks

Go to Shifter Tasks page

Beam operation

Go to Beam Operation page

Labview operation

Go to Labview Operation page

EUDAQ operation

Go to EUDAQ Operation page

Monitoring

Go to Monitoring page

Offline Data Analysis

Go to Offline Data Analysis page


CategoryHCAL


AHCALTestBeamCERN2015 (last edited 2017-01-05 13:06:08 by AmbraProvenza)