This pages describes in detail communication protocol, which is used in the HDMI DAQ chain. It consist of CCC <-> LDA specification, LDA <-> DIF specification, and LDA <-> PC specifications.

HDMI pinout

Following pins are used (lower pin number in the per is positive (_p) higher is negative (_n)):

pins

calice label

ahcal

CCC<=>LDA

purpose LDA <=>CCC

direction

1-3

clk

clk

clk

clk

CCC -> DIF

4-6

DL2D

fast commands

fast commands

data + fast commands

CCC -> DIF

7-9

DD2L

busy

busy

busy

DIF -> CCC

10-12

SPD2L

data

(not used)

data

DIF -> LDA

15-16

SPL2D

validation

validation

validation

CCC -> DIF

shortcuts:

CCC -> LDA Fast commands

Original communication protocol is described here: http://www.hep.manchester.ac.uk/u/mpkelly/calice/lda/Calice_LDA_Overview.html Fast commands are currently sent serially as 1 stop bit, 16 bit serial (LSB first), 2 stop bits, 10 MBits/s. Following commands are implemented:

command

hex UART code

8b10b code (future)

comment

start acquisition

0xE311

K28.3 + D2.1

stop acquisition

0xE313

K28.3 + D2.3

synchronize

0xE000

K28.0 + D0.0

Synchronize phases of 5 MHz derived clocks among layers

recover reciever

0x0000

--

debug only

LDA -> DIF data packets

The data is transferred serially in a same was as fast commands of CCC: 1 stop bit, 16 bit serial (LSB first), 2 stop bits, 10 MBits/s. Both fast commands and standart packets are sent via the same line.

field

PACKETTYPE

PACKETID

TYPEMODIFIER

SPECIFIER

DATALENGTH

DATA

CRC

bits

16 b

16 b

16 b

16 b

16 b

Length * 8b (16b aligned)

16 b

defaults

0xCC02

-

-

-

-

-

0xABAB

= TCP <-> LDA packets = The LDA is responsible for sending packets to the proper LDA port and for collecting+merging packets from DIFs. The LDA therefore adds additional header to the packets with some status flags and routing information. The LDA itself has its own address space, where parameters of the LDA can be set.

standart commands to the DIF

packet header

LDA_packet

LENGTH

ADDRESS1 (16 bit, little endian)

packet_data

CRC(0xABAB)

32 bits, little endian

16 bit, little endian

16b aligned, little endian

16 bits, 0xABAB

ADDRESS1[15:0]

meaning

0xFFxx

broadcast to all ports (address is changed to 0xCC02 when it is sent to DIF)

0x00xx - 0x5Fxx

a standard command to be sent to a specific port number from the range of 0x00 to 0x5F (ports 0 to 95)

0x60xx - 0x7Fxx

reserved

0x80xx

read from a LDA register

0x81xx - 0x82xx

reserved for setting and clearing bits from the LDA register

0x83xx

Write to the LDA register

LDA register address space

When LDA register is addressed, packet_data[15:0] is used for further addressing

packet header

LDA_packet

LENGTH

ADDRESS1 (16 bit, little endian)

ADDRESS2

packet_data

CRC(0xABAB)

32 bits, little endian

16 bit, little endian

16 bit, little endian

16b, little endian

16 bits, 0xABAB

where the ADDRESS2 has following meaning

ADDRESS2[15:0]

meaning

0x00yy - 0x5Fyy

individual system configuration port is addressed (ports 0 to 95)

0x80yy

fpga configuration port is addressed (1st Kintex in case of Wing-LDA)

0x81yy - 0x83yy

Individual kintexes for wing-LDA (2nd to 4th kintex)

0x90yy

Mars module configuration (only Wing-LDA)

0xFFyy

broadcast to all configuration ports

yy is the local subaddress

Packet Examples

Broadcast a command:

0x0000000C

length 12

0x0F0FFF02

0x0F0F=packetID, 0xFF02=broadcast

0x00040012

0x0004=Specifier (turn VDAC on), 0x0012=Modyfier (power_on)

|| 0xABAB0000 ||0xABAB=CRC, 0x0000=length 0(= no data field)

Disable all ports:

0x00000008

length 0x08

0xFF008302

0xFF=all ports, 0x00=port configuration address; 0x8302: write to LDA register

0xABAB0000

0xABAB="CRC", 0x0000=new value of the register

Disable port number 7:

0x00000008

length 0x08

0x07008302

0x07=port 7, 0x00=port configuration address; 0x8302: write to LDA register

0xABAB0000

0xABAB="CRC", 0x0000=new value of the register

Enable port number 7:

0x00000008

length 0x08

0x07008302

0x07=port 7, 0x00=port configuration address; 0x8302: write to LDA register

0xABAB0000

0xABAB="CRC", 0x0001=new value of the register(enable)

Set a ROC counter:

0x00000008

length 0x08

0x80068302

0x80=System_Port (Kintex1 system port for Wing-LDA), 0x06=system port address (ROC), 0x8302: write to LDA register

0xABAB1234

0xABAB="CRC", 0x1234=new value of the ROC

DIF -> LDA packets

a header is added to every packet, that is received from DIF and generated inside LDA:

field:

STATUS

PORT#

LDA#

(reserved)

ROC

Length

bits:

63:48

47:40

39:32

31:24

23:16

15:0

Status bits

0

ERROR_RX_PACKET_FORMAT

some unexpected data in the packet was found

1

ERROR_RX_PACKETID

Packet ID was not as expected

2

ERROR_RX_PACKET_ORDER

The readout packet order is mixed-up

3

ERROR_RX_CHAINSOURCE_MISMATCH

The merged readout packet was merget from different chain source or different asic number or both

4

ERROR_RX_TIMEOUT0

intra-packet timeout occurred

5

ERROR_RX_TIMEOUT1

inter-packet timeout occurred

6

ERROR_RX_LENGTH_OVERFLOW

the length of the packet overflew

7

ERROR_RX_CRC

CRC field of the packet doesn't match the calculated one

8..10

reserved

11

STATUS_TIMESTAMP

This is a timestamp packet

12

STATUS_CONFIG_PACKET

This is an LDA configuration packet

13

STATUS_MERGED_PACKET

(default:1) - the DIF readout packets are configured to be merged

14

STATUS_ROP_ASIC

This is a SPIROC readout, which can be decoded from gray

15

STATUS_ROP

This is a DIF readout packet

ASIC Readout packet

the packets are merged in the LDA into following packet:

TIMESTAMP packets

timestamp packets consist of 3 64-bit words:

bits:

63:56

55:48

47:40

39:32

31:24

23:16

15:8

7:0

WORD1:

STATUS (0x0800)

PORT# (0xA0)

LDA#

(reserved)

ROC

Length

WORD2:

TRIGID/ROC

(reserved,0x00)

TYPE

TIMEPACKET_STRING[31:0]=0x54494D45

WORD3:

CRC=0xABAB

TIMESTAMP[47:0]

type

shortly

TRIGID/ROC

0x01

ACQ_START

ROC number of acq cycle, that just started

0x02

ACQ_STOP

ROC number of acq cycle, that just started

0x03

SYN

ROC number of the last acq cycle

0x10

TRIGID

new TriggerID

0x11

ROC

new ROC number

0x20

BUSY_FALL

ROC number of previous acq cycle

0x21

BUSY_RISE

ROC number of the current acq cycle


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DAQ Section/AHCAL_HDMI_communication_protocol (last edited 2017-06-23 12:53:53 by JiriKvasnicka)